1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for forming an inductor in a semiconductor device.
2. Discussion of Related Art
An inductor being a passive device in RFCMOS, Bipolor/SiGe, BiCMOS semiconductor devices is formed by means of a damascene process as the devices are higher integrated.
A conventional method for forming an inductor in a semiconductor device will now be described with reference to FIG. 1A to FIG. 1C.
FIG. 1A to FIG. 1C are cross-sectional views for explaining a conventional method for forming an inductor in a semiconductor device.
Referring to FIG. 1A, an interlayer insulating film 12 is formed on a semiconductor substrate 11 in which a predetermined structure is formed. A photoresist pattern (not shown) is formed on the interlayer insulating film 12 and is then etched using an etch mask, thus forming a trench through which a predetermined region of a semiconductor substrate 11 is exposed.
By reference to FIG. 1B, an anti-diffusion film 14 and a copper seed layer 16 are formed on the entire structure. A copper layer 18 is then formed by means of an electroplating process, thus filling the trench. At this time, an electroplating process is implemented using a chemical catalyst.
Referring to FIG. 1C, the copper layer 18, the copper seed layer 16 and the anti-diffusion film 14 are polished by means of a polishing process such as a CMP process, so that a copper layer 18 of the inductor is formed.
Recently, as the degree of integration in semiconductor devices is increased, copper (Cu) has been widely used as a material of the inductor 18. In order to facilitate the use of copper, a damascene process is also used as described above. In order to obtain desired quality factors of the copper inductor 18, Cu lines of several μm in thickness are required. If theses copper inductor lines are implemented by means of the damascene process, there are difficulties in each process as follows.
Firstly, a thickness of an insulating film used in a typical semiconductor process is about 1 μm. The inductor 18, however, has to be formed in thickness of 2˜3 μm or more, i.e., the interlayer insulating film 12 has to be formed in thickness of 2˜3 μm or more. If the interlayer insulating film 12 is formed thickly as such, there are problems in the throughput of an apparatus, control of particles and stress and so on.
Secondly, an interlayer insulating film 12 having a thick thickness of 2˜3 μm has to be etched in order to form a trench pattern a. Thus the manufacturing cost is increased due to increased throughput and lengthened etch time.
Thirdly, the trench a has to be filled by an electroplating method with the anti-diffusion film 14 and the seed layer 16 formed along the surface of the first insulating film 12. Accordingly, defects such as void or seam are generated at portions where the line width of the inductor 18 is narrow due to conformal filling, as shown in FIG. 1C. This makes stability of the process difficult.
Fourthly, the metal layer 18 has a very great step and is formed very thickly about 3 to 5 μm. Polishing this metal layer 18 through a chemical mechanical polishing process is very difficult and requires lots of time, which adversely affects productivity and cost. Therefore, there is a problem that the cost unit is significantly increased.